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A 50-mW 14-bit 2.5-MS/s /spl Sigma/-/spl Delta/ modulator in a 0.25 /spl mu/m digital CMOS technology

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3 Author(s)
Balmelli, P. ; Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland ; Qiuting Huang ; Piazza, F.

A 5/sup th/-order single-loop /spl Sigma/-/spl Delta/ modulator has been implemented in a 0.25 /spl mu/m digital CMOS process, where the supply voltage is only 2.5 V and the capacitor option is not available. A tri-level quantizer is used to improve loop stability. The sampling frequency of the modulator is 80 MHz and the oversampling ratio is 32. Measured over a 1 MHz signal bandwidth, dynamic range is 86 dB, peak SNR is 80 dB and peak SNDR is 78 dB. The modulator consumes only 50 mW.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000