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Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS

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5 Author(s)
Wakimoto, T. ; NTT Lifestyle & Environ. Technol. Labs., Kanagawa, Japan ; Hatano, T. ; Yamaguchi, C. ; Morimura, H.
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To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35-/spl mu/m CMOS process, the up-conversion mixer core operates with a supply voltage of 0.5 V and a supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from a 1-V supply in the same band. The conversion gain is 6 dB and the 3rd-order input-referred intercept point (IIP3) is +5 dBm.

Published in:
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference: 15-17 June 2000

Page(s):
98 - 99
Meeting Date :
15 Jun 2000-17 Jun 2000
Print ISBN:
0-7803-6309-4
INSPEC Accession Number:
6715272
Conference Location :
Honolulu, HI, USA
Digital Object Identifier :
10.1109/VLSIC.2000.852861
Product Type:
Conference Publications

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