Referenced Items are not available for this document.
The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.
Published in:
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Date of Conference: 15-17 June 2000
- Page(s):
- 70 - 71
- Meeting Date :
- 15 Jun 2000-17 Jun 2000
- Print ISBN:
- 0-7803-6309-4
- INSPEC Accession Number:
- 6715267
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.2000.852854
- Product Type:
- Conference Publications
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