The paper analyses the mathematical expression of digital-to-analog conversion and explains the physical realization of a binary DAC by means of dividing current, whereby the resistor network of the quaternary DAC is proposed. By using quaternary signal decode, a novel Π-type resistor network is derived. Compared with the conventional T-type resistor network, a quarter of resistors in this network can be saved and the precision is ensured
Published in:
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Date of Conference: 2000