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Implementation of multiple-valued multiplier on GF(3m) using current mode CMOS

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4 Author(s)
Hyeon Kyeong Seong ; Dept. of Comput. Sci. & Eng., Sangji Univ., South Korea ; Jai Seok Choi ; Boo Sik Shin ; Heung Soo Kim

The multiplication algorithm of two polynomials on finite fields GF(3m) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(33) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 μm standard CMOS device parameters, 20 μA unit current level and 3.3 V VDD voltage supply

Published in:

Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

Date of Conference:

2000

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