By Topic

Wafer level chip scale packaging (WL-CSP): an overview

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
P. Garrou ; Dow Chem. Co., Res. Triangle Park, NC, USA

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. RambusTM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages

Published in:

IEEE Transactions on Advanced Packaging  (Volume:23 ,  Issue: 2 )