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Multiple-fault detection for the balanced and unbalanced conditional-sum adders

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2 Author(s)
C. Arjhan ; Div. of Electr. & Comput. Sci. & Eng., Florida Inst. of Technol., Melbourne, FL, USA ; R. G. Deshmukh

In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed

Published in:

Southeastcon 2000. Proceedings of the IEEE

Date of Conference: