By Topic

Extension of PCI bus to 21 slots using GTLP transceiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Siegl, C. ; Fairchild Semicond. Corp., USA ; Klem, R.C.

The PCI (peripheral component interconnect) bus in various form factors is the most frequently implemented interface for a broad class of computing application architectures in new designs. While originally developed as a local interconnect bus for the PC market (around 1994 it became the de facto standard for high speed device interconnect on PC planers), the technology has been widely adopted in both proprietary, as well as standard (CompactPCI(R) and CardBUS for example) implementations. These implementations are all limited in the number of slots supported, 4 slots in the PC and 8 slots for CompactPCI(R). This paper demonstrates how, through the application of IWS (incident wave switching) with GTLP (gunning transceiver logic plus) transceivers and an optimized backplane, the CompactPCI(R) (sometimes abbreviated to cPCI) standard can be extended to 21 slots at 33 MHz and to 14 slots at 66 MHz

Published in:

Southeastcon 2000. Proceedings of the IEEE

Date of Conference: