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Efficient parallel multicast ATM switch

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2 Author(s)
Deng, Y.-W. ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chen, W.T.

A novel multicast switch architecture with high throughput performance and low hardware complexity is proposed. The storage complexity of the translation tables required by the copy network is improved from O(N2) to O(N). The throughput performance of the proposed switch architecture is very close to 100% when more than five multicast switching modules (MSMs) are used. The proposed multicast switch architecture is composed of multiple MSMs arranged in parallel. An MSM is composed of a copy network and a routing network. A multicast bounded-fanout principle is proposed which states that the overflow probability of a copy network can be reduced to an acceptable level if the output capacity of the copy network is properly expanded. Instead of building a very large expanded copy network, multiple small copy networks are arranged in parallel to effectively expand the aggregate output capacity of the copy networks. A simple copy network architecture is proposed which guarantees that all cell copies are generated at predefined outlets so that the storage complexity of the translation tables is of O(N). A Batcher-banyan based routing network is adopted to switch cell copies generated by the copy network. A 10-9 cell loss probability can be achieved when twelve MSMs are used in the proposed switch

Published in:

Communications, IEE Proceedings-  (Volume:147 ,  Issue: 2 )