By Topic

Reducing test application time for built-in-self-test test pattern generators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
I. Hamzaoglu ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; J. H. Patel

This paper presents a new technique, called C-compatibility, for reducing the test application time of the counter-based exhaustive built-in-self-test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS 85 and full scan versions of the ISCAS 89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counter-based exhaustive BIST pattern generators

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference: