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A low-speed BIST framework for high-performance circuit testing

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4 Author(s)
Speek, H. ; MESA Res. Inst., Twente Univ., Enschede, Netherlands ; Kerkhoff, H.G. ; Shashaani, M. ; Sachdev, M.

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference:

2000