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Test data compression for system-on-a-chip using Golomb codes

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2 Author(s)
A. Chandra ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; K. Chakrabarty

We present a new test data compression method and decompression architecture based on Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SOC). The major advantages of Golomb codes include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS benchmark circuits and to two industrial production circuits. We also use analytical and experimental means to highlight the superiority of Golomb codes over run-length codes

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VLSI Test Symposium, 2000. Proceedings. 18th IEEE

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