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Virtual scan chains: a means for reducing scan length in cores

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3 Author(s)
Jas, A. ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Pouya, B. ; Touba, N.A.

A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a normal scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a normal scan chain. The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data and fewer scan shift cycles. The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator. It is done by using LFSRs to “expand” the shorter virtual test vector into a full test vector. Results indicate that virtual scan chains can be designed which are several times shorter than the real scan chains inside the core

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference: