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Thermal characteristics of submicron vias strongly impact reliability of multilevel VLSI interconnects. The magnitude and spatial distribution of the temperature rise around a via are important to accurately estimate interconnect lifetime under electromigration (EM), which is temperature dependent. Localized temperature rise can cause stress gradients inside the via structures and can also lead to thermal failures under high current stress conditions, such as electrostatic discharge (ESD) events. This letter reports the first use of a novel thermometry technique, scanning Joule expansion microscopy, to study the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress. Measurement of the spatial distribution of temperature rise around a submicron via is reported with sub-0.1 μm resolution, along with other thermal characteristics including the thermal time constant.