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Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

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9 Author(s)
Jinju Lee ; Beckman Inst. for Adv. Sci. & Technol., Illinois Univ., Urbana, IL, USA ; Kangguo Cheng ; Zhi Chen ; Hess, K.
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We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Published in:

Electron Device Letters, IEEE  (Volume:21 ,  Issue: 5 )

Date of Publication:

May 2000

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