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A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

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6 Author(s)
Miyazaki, M. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ono, G. ; Hattori, T. ; Shiozawa, K.
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Substrate bias is continuously controlled from -1.5 V (backward bias) to 0.5 V (forward bias) to compensate for fabrication fluctuation, supply voltage variation, and operating temperature variation. A speed-adaptive threshold-voltage (SA-Vt) CMOS with forward bias is used in a 4.3M transistor microprocessor. The SA-Vt CMOS with forward bias occupies 320/spl times/400 /spl mu/m/sup 2/ and consumes 4 mA. The processor provides 400 VAX MIPS at 1.5 to 1.8 V with 320 to 380mW dissipation. It achieves >1000-MIPS/W performance.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000