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A 125 MHz 1 GIPS at 1.3 V 1 W microprocessor with single-chip tightly-coupled multiprocessor architecture and low-voltage circuits is targeted to high-performance and low-power embedded systems, especially smart information terminals. This paper shows an entire chip diagram integrating four tightly-coupled processors. Each processing element (PE) is in-order two-way issue superscalar with two ALU pipelines. A power-management unit (PMU) cuts off the leakage current of each power-control domain independently using dedicated power switches.
Date of Conference: 9-9 Feb. 2000