By Topic

An 8 ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/ RAM)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)
Agata, Y. ; Matsushita Electr. Ind. Co. Ltd., Japan ; Motomochi, K. ; Kagenishi, Y. ; Fukushima, Y.
more authors

Recent multimedia applications and personal computers require enhanced memory systems. 3D-graphics and networking require faster random cycle and lower latency megabit-scale RAMs. However, the random cycle time of conventional DRAM is too slow and embedded SRAM area is too large to integrate high-density RAM on a chip. The fast random cycle low-latency embedded RAM macro reported here uses a dual-port interleaved DRAM architecture (D/sup 2/RAM). D/sup 2/RAM reduces random cycle time from 50 ns (20 MHz) of conventional DRAM to 8 ns (125 MHz) on a test chip with a 0.25 /spl mu/m embedded DRAM process. Key technologies are (1) interleaved open bitline operation with dual-port memory cell architecture, (2) two-stage pipelined circuit operation and (3) write before sensing (WBS).

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000