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DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs

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6 Author(s)
Yoshimura, R. ; Dept. of Electron. & Inf. Syst., Osaka Univ., Japan ; Tan Boon Keat ; Ogawa, T. ; Hatanaka, S.
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A new bus architecture is described which is suitable for a parallel processing system without complexity of interconnection, and also drastically reduces the I/O pin count, which is highly desirable for future gigascale integrated systems. The architecture is based on the direct sequence code division multiple access (DS-CDMA) technique.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000