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In direct sequence code division multiple access (DS-CDMA), matched filters calculate the cross-correlation function of a received signal spread by a pseudo-random noise (PN) sequence and a replica PN sequence. A matched filter like this can be viewed as a finite impulse response (FIR) filter with a PN sequence used as the binary tap weights, minimizing search and synchronization times in DS-CDMA receivers. This paper introduces an approach for implementing matched filters based on recycling integrator correlators (RICs) that use a sensible combination of analog and digital processing to minimize area and power consumption. The matched filter is organized by combining an array of RICs, a cyclic shift register which stores a PN sequence, and a rotary multiplexer which transfers the correlation values one by one. This implementation provides: 1) an input analog signal processing capability without the need of a fast ADC; 2) an already digitally-coded output stream; 3) small capacitor ratios for the switched-capacitor (SC) integrators; and 4) minimum die-area and current consumption for the available technology and the spreading ratio, that is, the length of the PN sequence. The fabrication process is a 0.35 /spl mu/m CMOS double-metal, double-poly process. The chip occupies 22.8 mm/sup 2/ and dissipates 23 mW with a 1.8 V power supply.