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This microprocessor implements the PowerPC/sup TM/ architecture and incorporates AltiVec/sup TM/ technology. Features include processor pipeline depth changes and memory subsystem enhancements for total system performance improvements through frequency scaling and sustained IPC. The processor is in 0.18 /spl mu/m 1.5V twin-well CMOS with local interconnect and 6 layers of copper interconnect. Using semi-custom flow, the chip includes a mixture of custom circuit macros for high-performance and high-density, and off-the-shelf datapath elements with standard cell control logic to enhance designer productivity. Circuits are static or 2-phase domino precharged, both footed and unfooted. The 2-phase clocking is augmented by delayed-reset clocks for unfooted circuits and by local delays in array macros. Each clock rising edge or self-timed delay has programmable adjustments for debug. Caches include fuse programmable row and column redundancy.
Date of Conference: 9-9 Feb. 2000