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The implementation of new wireless communication standards often requires the design of new hardware capable of processing special algorithms. One approach of tackling the problem is the usage of dedicated hardware, optimized towards the corresponding algorithm, together with a DSP. However this may cause overhead in data transfers (DSP <-> ASIC) and requires additional control hardware and memories. The full design process including simulation and debugging of the whole system can be very time consuming. In this paper we avoid such problems by utilization of a new concept for application tailored DSPs. The architecture supports scaling and the inherent flexibility allows for the adaption to new algorithms. Examples such as equalization and the future wireless W-CDMA standard UMTS has been used to prove the applicability of the structure, In addition, the time-to-market factor can be significantly reduced.