Early branch prediction circuit for high performance digital signal processors

In this paper, design and VLSI implementation of an Early Branch Prediction (EBP) circuit, based on a variation of Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2[log n/2]+1), and high modularity. This design out performs all the EBP designs presented so far. For 64 bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2 /spl mu/ technology under typical conditions. Simulation and layout results for 0.2 /spl mu/ CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results.