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Parasitic extraction methodology for insulated gate bipolar transistors

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2 Author(s)
Trivedi, M. ; Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA ; Shenai, K.

This paper presents a methodology for extraction of the electrical package parasitics of insulated gate bipolar transistor power modules using simple electrical measurements. Nonidealities of device performance in zero-voltage and zero-current switching are exploited to obtain the parasitic collector and emitter inductance. Simple impedance measurements are performed to extract gate inductance and resistance. The extraction methodology is validated by comparing two-dimensional numerical simulation results including package parasitics with measured data. A close match between the two indicates the robustness of the extraction procedure

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Applied Power Electronics Conference and Exposition, 2000. APEC 2000. Fifteenth Annual IEEE  (Volume:2 )

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