By Topic

Fault simulation in CMOS VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zaghloul, M.E. ; Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., Washington, DC, USA ; Gobovic, D.

In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults, such as transistor stuck-closed, floating line faults and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:138 ,  Issue: 4 )