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IC test structures for multilayer interconnect stress determination

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5 Author(s)
S. A. Smee ; Dept. of Mech. Eng., Maryland Univ., College Park, MD, USA ; M. Gaitan ; D. B. Novotny ; Y. Joshi
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A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.

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IEEE Electron Device Letters  (Volume:21 ,  Issue: 1 )