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The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 /spl Aring/ have been studied. In order to minimize the junction leakage current, the thickness of the CoSi/sub 2/ layer should he controlled under 300 /spl Aring/ and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi/sub 2/ layer into the channel direction when the gate spacer length was larger than 400 /spl Aring/.