Improving the efficiency of parasitic extraction and simulation of 3D interconnect models

As VLSI circuit speeds and density continue to increase, the need for accurately modeling the effects of three-dimensional interconnects has become essential to accurate chip and system design. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, efficiency requirements imply that those models must be kept very compact without compromising accuracy. In this paper we describe a technique based on the combination of two model order reduction algorithms applied to an integral equation approach to efficiently generate accurate, yet low order models of the impedance of 3D interconnect structures. The models thus generated are amenable to direction inclusion in standard circuit simulators.