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Jitter estimation methodology for clock chips

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3 Author(s)
S. K. Maheshwari ; CYPRESS Semicond., India Design Center, Bangalore, India ; G. S. Visweswaran ; R. S. Krishanan

A simulation methodology is developed for clock chips to predict their AC performance more accurately. Power bus modeling is shown to lead to more accurate and predictable jitter values. Jitter variation is plotted for a typical set of 2CPU-7PCI simultaneously switching pads, for the variation in inductance, capacitive load and frequency

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VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: