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On the transistor sizing problem

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1 Author(s)
Das, A. ; Motorola India Electron. Ltd., Bangalore, India

This paper introduces a new transistor sizing technique for timing optimization in a transistor level netlist. Starting from an initial solution, the widths of the transistors in the netlist are tuned iteratively to meet the specified timing constraints. Efficient heuristics to significantly improve the run time performance are outlined. The improvement of timing and area performance are demonstrated with several real circuits

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: