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A transistor level placement tool for custom cell generation

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4 Author(s)
R. K. Dash ; Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India ; T. Pramod ; V. Vasudevan ; M. Ramakrishna

In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method

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VLSI Design, 2000. Thirteenth International Conference on

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