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Delay-constrained area recovery via layout-driven buffer optimization

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1 Author(s)
Murgai, R. ; Fujitsu Lab. of America Inc., Sunnyvale, CA, USA

During logic optimization/mapping, a designer or a synthesis tool constructs buffer trees to improve the delay characteristics of the circuit. However, since wire delays and capacitances are not known, the timing information is inherently inaccurate at this stage. After cells have been placed and nets routed, wire loads and delays are known more accurately. It is possible then that buffer trees generated earlier can be improved, resulting in better delay and area for the design. Large, industrial digital designs can have as many as 30% cells that are buffers. Optimizing (deleting and/or replacing) buffers can lead to significant area and/or delay reduction. In this paper, we address the problem of recovering maximum possible area of a mapped, approximately placed and globally routed digital design via buffer optimization without degrading the circuit timing or overloading the cell pins. We propose an exact, layout-driven algorithm to minimize the area of an extended net without increasing the circuit delay, for both buffer deletion and buffer insertion/deletion. Our key algorithmic contribution is to organize all possible buffer insertion/deletion choices with identical area components in a sorted array and to exploit that in devising efficient solution combining, merging, and pruning techniques. We propose and compare various, schemes for applying the single-net algorithm to an entire design. The most formidable challenge is to handle large designs in a reasonable time under the memory constraint. On average, 50.8% of the buffer area of already optimized, real industrial designs could be reclaimed without degrading the circuit delay or overloading any cell pins

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: