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Design partitioning on single-chip emulation systems

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2 Author(s)
A. Ejnioui ; Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA ; N. Ranganathan

In this paper, we address the problem of partitioning a large design on a reconfigurable single-chip emulator under resource constraints. First, we extract an acyclic flow graph of the design to be emulated. Then, we model the problem as an integer linear programming problem (IP) based on the acyclic flow graph of the design where the structure of the assignment and precedence constraints produce a tight formulation. This formulation is suitable for small designs. For larger designs, we generate a smaller formulation of the integer programming problem based on a reduced form of the acylic graph. Then we use an incremental iterative technique to keep the problem formulation as small as possible. To partition a large design, our algorithm uses two distinct steps with different objectives. In the first step, we minimize the number of cycles needed to schedule every lookup table (LUT) in the circuit. Then flip-flops (FFs) are inserted into the appropriate cycles of the schedule in the second step. Experiments are conducted on small and moderately large circuits from the MCNC Partitioning93 benchmark suite. The obtained results show that our algorithm produces optimal partitioning schedules

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VLSI Design, 2000. Thirteenth International Conference on

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