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Combining background memory management and regular array co-partitioning, illustrated on a full motion estimation kernel

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3 Author(s)
Schaffer, R. ; Inst. of Circuit & Syst., Tech. Univ. Dresden, Germany ; Merker, R. ; Catthoor, F.

In this paper an approach is presented to combine the design of background memory architectures and processor arrays for data dominated real-time applications. The formalized data transfer and storage exploration (DTSE) approach of IMEC involves a stepwise methodology for the design of a low-power small-size background memory organisations, meeting real-time constraints. The systematic space-time transformation and the subsequent copartitioning approach of the Dresden University of Technology allow the design of realistic processor arrays adapted to a given memory architecture. However, neither methodology can derive on its own the complete solution of a fully optimized memory organisation, combining background and foreground memory. Extensions to enable this important problem will be presented here. First, both complementary methodologies will be summarized. Next, the main emphasis in this paper will be on the approach to design the processor array within the context of an already optimized and hence given memory architecture. The feasibility of the proposed combination is demonstrated on a representative test-vehicle for an important class of applications, namely a full motion estimation kernel in MPEG

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VLSI Design, 2000. Thirteenth International Conference on

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