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A low power 900 MHz register file (8 ports, 32 words×64 bits) in 1.8 V, 0.25 μm SOI technology

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5 Author(s)
Joshi, R.V. ; Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Hwang, W. ; Wilson, S. ; Shahidi, G.
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This paper shows full functionality of a low power 900 MHz dynamic register file (6 Read and 2 Write ports, 32 wordlines×64 bitlines). Such a register file is designed for bulk silicon technology but is fabricated in 0.25 μm Silicon on Insulator (SOI) technology without any body contacts. This paper also proposes a new method to extract the performance gain (which is limited by the tester speed) of a register file in bulk and SOI technology based on internal picoprobe measurements along the critical path. Based on the hardware and simulation data the register file is capable of functioning at 900 MHz for read and write operations in a single cycle. The register file can even function above 1 GHz for read operation. A power reduction of 8-12% is realized for SOI over bulk technology especially at higher frequencies

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VLSI Design, 2000. Thirteenth International Conference on

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