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A chip design for binary and binary morphological operations

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3 Author(s)
K. M. Shaaban ; Dept. of Electr. Eng., Assiut Univ., Egypt ; S. A. Ali ; Y. B. Mahdy

A design for a chip to perform binary and binary morphological operations is provided. The chip is intended to be a part of a pipeline machine controlled by a general purpose processor. It could process 25512×512 pixel frames per second in one pixel per clock cycle rate. In real time application an array of this chip could be used, leading to a less expensive design than using an array of general DSP chips. The functionality of the chip is programmable by changing the flow of data between the internal units using a multiplexer and demultiplexer set. A 15-bit control register is used to set the flow path and consequently the operation

Published in:

Information Intelligence and Systems, 1999. Proceedings. 1999 International Conference on

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