By Topic

Asynchronous design for programmable digital signal processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
T. H. -Y. Meng ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; R. W. Brodersen ; D. G. Messerschmitt

A systematic procedure for designing fully asynchronous programmable processors from an architectural description is described. Design issues such as pipelining, interconnection circuit specifications, data flow control, program flow control, feedback and initialization, I/O (input/output) interface, and processor architecture are discussed. The system-level tradeoffs of using synchronous design versus asynchronous design are addressed. Simulation results of an asynchronous version of a commercial digital signal processor are given

Published in:

IEEE Transactions on Signal Processing  (Volume:39 ,  Issue: 4 )