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Architecture of the Atlas chip-multiprocessor: dynamically parallelizing irregular applications

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2 Author(s)
Codrescu, L. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Wills, D.S.

An important research direction for future microprocessors is the single-chip multiprocessor. The drawbacks of this approach are that many important applications cannot be automatically parallelized and that performance suffers with “dusty-deck” binaries. This paper details a single-chip multiprocessor that engages a combination of aggressive speculation techniques to enable the dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar execution) and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning called MEM-slicing, and includes an extremely aggressive correlated value predictor. Several new microarchitectural structures to manage inter-thread dependencies are described. Simulations show that sequential programs are amenable to this form of execution. Over SPECint95, an average speedup of 3.4 is achieved on 8 processors due entirely to the exploitation of thread level parallelism

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Computer Design, 1999. (ICCD '99) International Conference on

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