By Topic

Yield optimization by design centering and worst-case distance analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Samudra, G.S. ; Center for Integrated Circuit Failure Anal. & Reliability, Nat. Univ. of Singapore, Singapore ; Chen, H.M. ; Chan, D.S.H. ; Ibrahim, Y.

Process variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. The paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the worst-case distance analysis, design centering and gradient-dependent techniques. One circuit example is presented to demonstrate the optimization scheme

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference: