Improving microcontroller power consumption through a segmented gray code program counter

This paper introduces a new segmented gray code for microprocessor program counters that exploits the switching activity enhancements of a gray code on high capacitive microcontroller address lines while decreasing the area requirement of the necessary counter hardware. For higher bit widths gray code incrementers tend to explode in complexity compared to binary counters. The presented concept overcomes this problem by localizing the global scope of the common gray code. A method is developed to evaluate the valid gray codes in order to find the optimal one concerning area consumption of its incrementer. Resulting from this evaluation a segmented gray code is presented for which the area and power consumption is lower than for a binary incrementer. This code used for a microprocessor program counter leads to a decrease of the switching activity on the address bus by 25-30% while at the same time decreasing the area and power consumption of the program counter by about 10%.