Design and implementation of a parallel weighted random pattern and logic built in self test algorithm

An increase in chip densities has led to a significant increase in test generation and fault simulation times. Analysis of various test methodologies has shown that logic built in self test (LBIST) and weighted random pattern test (WRPT) are a significant portion of the execution time. Several parallel algorithms have been proposed to reduce run times for ATPG. This paper describes, for the first time, the parallelization of the LBIST and WRPT algorithms. Results on industrial circuits that range in size from 300,000 gates to about 1 million gates are presented. Previous works have published results on parallelization of deterministic testing and simulation for smaller circuits.