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A 4-bit Josephson computer ETL-JC1

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7 Author(s)
H. Nakagawa ; Electrotech. Lab., Ibaraki, Japan ; I. Kurosawa ; M. Aoyagi ; S. Kosaka
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The first computer operation of a 4-b Josephson computer, ETL-JC1 (Electrotechnical Laboratory-Josephson Computer no.1), designed using a reduced instruction set computer (RISC) architecture is described. In the experiment, the computer functions have been verified by executing a computer program installed in a Josephson read-only memory (ROM) at a low repetition frequency. To construct the computer, four Josephson LSI chips including a register and arithmetic logic unit, a sequence control unit, an instruction 1280-b ROM unit, and a 1-kb RAM unit were connected on a nonmagnetic printed circuit board. The Josephson LSI chips were fabricated using Nb/AlO/sub x//Nb tunnel junctions with 3- mu m design rules. The total power dissipation was 6.2 mW in the total circuit, which consists of 22000 junctions including regulators on every chip. On the basis of measurements of the delay times of the logic gates and the access times of the memory chips, it is expected that the program execution in the critical path can be carried out with a single central processing unit in less than 1 ns, resulting in 1 giga-instructions per second (GIPS).<>

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IEEE Transactions on Applied Superconductivity  (Volume:1 ,  Issue: 1 )