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A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

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2 Author(s)
Takase, S. ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; Kushiyama, N.

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach

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Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 11 )