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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

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6 Author(s)
D. Takashima ; Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan ; S. Shuto ; I. Kunishima ; H. Takenaka
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A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, a two-way metal cell-plate line and a cell-plate line shared with 16 cells, reduce cell-plate-line delay to 7 ns and reduce plate drive area to 1/5. The total cell-plate-line delay, including cell transistor delay due to eight cells in series, is reduced to 15 μs, in contrast to 30-100-ns delay of the conventional FRAM. The die size is reduced to 86% that of the conventional FRAM by reduction of the plate driver area and sense amplifier area, assuming the same memory cell size. A prototype 16-kb chain FRAM chip was fabricated using 0.5 μm rule one-polycide and two-metal CMOS process. The memory cell size was 13.26 μm2 using a 3.24-μm2 capacitor. Thanks to the fast cell-plate-line drive, the chain FRAM test chip has achieved the fastest random access time, 37 ns, and read/write cycle time, 80 ns, at 3.3 V so far reported. The chain FRAM has also realized Vdd min of 2.3 V and 1010 read/write cycles

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 11 )