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A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications

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18 Author(s)
A. Nozoe ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; H. Kotani ; T. Tsujikawa ; K. Yoshida
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A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm2 die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell Vth. The effect of adjacent memory cell's Vth is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell Vth. In the -5-75°C range, memory threshold Vth deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 11 )