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Application of a new laser scanning pattern wafer inspection tool to leading edge memory and logic applications at Infineon Technologies

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6 Author(s)
T. Reuter ; Infineon Technol., Dresden, Germany ; U. Bohmler ; S. Steck ; M. McLaren
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A new patterned wafer laser-based inspection tool has been introduced to the market place, incorporating double darkfield laser scanning technology. Developed from a well-known production-proven platform, the new system is intended to provide the sensitivity required for 0.18 μm design rules, with extendibility to 0.13 μm. The inspection technology combines low angle laser illumination with dual darkfield scattered light collection channels. Enhancements to the illumination and collection optics have allowed for improved defect sensitivity and capture; and enhanced software algorithms have provided greater compensation for process variation, further increasing defect capture. The sensitivity performance and production worthiness of the tool were evaluated at Siemens Microelectronics Centre and the key results are presented. Both memory and logic products were evaluated, including memory products with 0.2 μm design rule, and logic products with 0.2 μm design rule. Layers from the front-end and back-end of the manufacturing process were evaluated. On memory products, sensitivity to defects occurring during capacitor and isolation trench formation was demonstrated, including etch defects deep in the trench structures and sub 0.1 μm discrepancies in the formation of isolation trenches. Results from post-metal etch inspection demonstrated enhanced sensitivity in both array and periphery regions, largely achieved by exploiting the new ability to perform region-based optimisation, allowing full die area inspections. On logic products, surface foreign material less than 0.1 μm in diameter was detected amidst logic structures and, in the same inspection pass, etch residuals affecting the memory cache area were also captured. The machine was installed and operated in a high capacity wafer production environment and adhered to all specified throughput, up-time and reliability matrices throughout the evaluation period

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Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

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