Referenced Items are not available for this document.
Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can predict failing bitmap signatures and their frequencies for any memory circuit. The technique is demonstrated using a 0.25 μm SRAM technology. Results can be used for test optimization, redundancy planning, yield prediction, and determining process steps responsible for yield loss
Published in:
Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI
Date of Conference: 1999
- Page(s):
- 178 - 182
- Meeting Date :
- 08 Sep 1999-10 Sep 1999
- ISSN :
- 1078-8743
- Print ISBN:
- 0-7803-5217-3
- INSPEC Accession Number:
- 6512794
- Conference Location :
- Boston, MA
- Digital Object Identifier :
- 10.1109/ASMC.1999.798216
- Product Type:
- Conference Publications
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