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Predicting failing bitmap signatures for memory arrays with critical area analysis

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6 Author(s)
Segal, J.D. ; HPL Inc., San Jose, CA, USA ; Ho, T. ; Hodgkins, B. ; Misic, P.
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Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can predict failing bitmap signatures and their frequencies for any memory circuit. The technique is demonstrated using a 0.25 μm SRAM technology. Results can be used for test optimization, redundancy planning, yield prediction, and determining process steps responsible for yield loss

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Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

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