Skip to Main Content
A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is proposed. This redundancy saves an area of spare cells from 6% to 1.6% and improves chip yield from 50% to 80%. It provides high speed data path. An embedded DRAM macro adopting the redundancy achieves 200 MHz operation and provides 51.2 Gbit/sec bandwidth. It has been fabricated with 0.25 /spl mu/m technology.