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Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

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13 Author(s)
T. Namekawa ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; S. Miyano ; R. Fukuda ; R. Haga
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A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is proposed. This redundancy saves an area of spare cells from 6% to 1.6% and improves chip yield from 50% to 80%. It provides high speed data path. An embedded DRAM macro adopting the redundancy achieves 200 MHz operation and provides 51.2 Gbit/sec bandwidth. It has been fabricated with 0.25 /spl mu/m technology.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999