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Embedded DRAM for a reconfigurable array

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5 Author(s)
Perissakis, S. ; Div. of Comput. Sci., California Univ., Berkeley, CA, USA ; Joo, Y. ; Ahn, J. ; Dellon, A.
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A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999