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This paper describes a DRAM system for consistently reducing CPU wait cycles for an access to DRAMs in a cache-based memory hierarchy. An arithmetical address mapping circuitry and a pseudo dual-port DRAM access protocol provide a DRAM access without a bank conflict and high speed write-back accesses (write for dirty data and read for cache-line filling). Only two adders for the address mapping circuitry and a data-preload register in each DRAM are necessary for the implementation.
Date of Conference: 17-19 June 1999